Supra Turbo 28 with manual, disk and box
Supra Turbo 28, A500 version
Supra Turbo 28, A2000 version
Processor: 68HC000@28Mhz (with SRAM Cache)
FPU: None
MMU: None
Max Ram: None

The Supra Turbo 28 was available in two forms but is essentially the same device. The first version was mounted in a case and is designed to be attached to the side expansion slot of the A500/+. It also included a pass-through for attaching additional devices. The second version is simply the motherboard supplied without the case and this is designed to be connected to the A2000 CPU Fast Slot. Note, this unit is not compatible with early German manufactured A2000's with "4-Layer PCBs". In theory it should be possible to remove the A500 version from the case and install it in an A2000, although removal of the A500 edge connector may be necessary.


Boot Jumper

Enables or disables booting.

Machine Jumper

If the unit is being used in an A2000 then this jumper must be installed, otherwise it must be removed if the unit is connected to an A500/+

Option Jumper

If you have more than 4MB of Fast RAM, removing this jumper will disable caching of the upper 4MB of the Amiga's auto-config memory space ($00600000-009FFFFF). This will avoid certain cases, for example with Bridgeboards, which can lead to a stale cache on the Supra Turbo 28. This conflict/solution may also affect some RTG cards which attempt to read from the cache-capable memory address space.  Similarly, GVP Series II SCSI controllers fitted with onboard memory eventually lead to the corruption of the Supra Turbo 28's cache.

Technical Reason for Conflict: Commodore never made provision for hardware bus snooping on the Amiga expansion bus(es).  The Supra Turbo 28 attempts to hardware bus snoop the Zorro II expansion bus in order to maintain cache coherency.  Any activity on expansion board memory spaces which it can not detect transfers on causes a potential stale cache condition.  Bridgeboards fail when they are in a cachable memory space because the bridgecard's processor can change data in the shared memory undetected.  GVP Series II DMA transfers to onboard memory occur on non-CPU access cycles, so the bus snoop fails.  GVP Series II drivers =>V3.14 can use a feature in the GVPSCSICtrl tool to address the caching problem. 

Note also that ChipRAM cannot be cached for the same reason.  i.e. - Agnus moves data around, and it can not detect it.  The accelerator's cache will only work against FastRAM.


The unit can be enabled or disabled in software, or by the use of a jumper/switch. The setting of the jumper/switch sets the initial state of the unit at power on which can of course be changed by the software afterwards. The A2000 version may not have the physical switch attached, like the A500 version.

Page contributors: Allan Müller, Andrew Bowers, Andy Johnson, Dell Smith, Simon Vergauwen
Updated: 1/25/2020 . Added: 12/22/2004