Big Book of Amiga Hardware

A full length Zorro II 33C93A-based DMA-driven SCSI-II controller Card + 0-8MB of Zorro II AutoConfig memory. 

GVP sold this product under many marketing names (HC8, HC+8, A4008, and possibly more internationally), but they are all the same SCSI+RAM controller product based on the GVP DPRC custom DMA controller chip.

An internal 50pin connector and an external DB25 pin connector is provided for SCSI peripherals.  It has enough space to mount a hard drive on the card and has an LED header to connect to the A2000 case HD LED.  The Zorro II AutoConfing memory is populated in 2MB increments up to 8MB of RAM in the form of pairs of 1MBx8 30-pin SIMMs or as two 4MBx8 30pin SIMMS. 
 

Common Memory Jumper Settings.

Using 1mb simms (in pairs)

Additional 8MB configuration setting for Rev 4, 5, I, and II, (has J14) using 2x 4MBx8 SIMM in CN10/CN11.

Common Header/Jumper Functions (not all boards have every jumper)

The boards of this controller family may have appeared under several names based upon GVP and worldwide distributor marketing.  All are identical in function, excluding some minor updates in the later PCB revisions.  Most boards are trace-etched with GVP A2000-HC+8 Series II Rev x along the front edge.  The following are the changes over the course of the product line, based upon the PCB revisions:

Rev 1 - Early revision, limited distribution.  2-layer PCB, GVP logo not on the DPRC (has a Motorola (M) symbol and part number S38GC023FD02)
Rev 2 - Full production, 4-layer PCB (and all that follow are same), same DPRC as Rev 1.  DPRC pad expanded slightly.
Rev 4 - Gains U8 (see below) and J14 (2x 4MBx8 SIMM option), loses J13 (internal use, a clock source selection).
Rev 5 - Updated DPRC package silkscreen (gains GVP logo at some point), but no functional changes.
Rev I - PCB updated to support additional surface-mount components as a production cost reduction in some areas, gains J15 DTACK expansion bus signal pullup jumper option.
Rev II - All passives and chip logic are surface-mount.  Single pigtail power lead on most boards.  Gains silkscreen jumper settings table (may be on Rev I also).
 

PCB/Jumpers Details & Changes of Note

J3 - This undocumented jumper was for engineering test.  It forced AutoConfig to stop at the board and not configure it or any downstream boards.
J4 - This enables or disables the boot ROM.  Removing makes the ROM code dissappear from the card's AutoConfig _diag offset address.
J13 - This undocumented clock source jumper dissappeared after REV 2, as the default clock source was determined to be stable/the best.
J14 - Provided the additional memory selection option to use 2x 4MBx8 SIMMs, if available.  Appeared with PCB Rev 4.
J15 - DTACK Pullup - It was discovered that some early 4.x motherboards sometimes needed some addded pullup on the DTACK signal under some expansion bus loads.  Normally not needed if the motherboard was updated to C= Rev 4.4/4.5 spec.
U8 - Engineering added a 74F244 to the Rev 4 PCB and later to buffer address lines to the SIMM memory sockets.  A full 8x load of 8-chip SIMMs could load the address lines enough off the DPRC that the memory didn't respond fast enough.  Use 80ns RAM (or faster), or (prefereably) use the 2-chip variant (1Mx4 x 2 chips per module) of the 1MB 30-pin SIMM, if fully loading the Rev 1 & 2 boards.
CN2 - 50-pin internal SCSI ribbon connector
CN3 - 25-pin external DB25 SCSI interface connector.

*J10/11/12 - Option jumpers for the driver to read and adjust behavior, as needed.
- On early boards, J10 may not have worked well when read by the driver, so J11 was also read.  Prior to gvpscsi.device v3.14, the 33C93A is expected to be clocked at 7MHz (J2 on 1/2), and shorting J10/J11 indicates that 14MHz clocking (J2 on 2/3) is in effect.
- On boards shipped with gvpscsi.device 3.14 and later, the 33C93A is expected to be clocked at 14MHz (J2 on 2/3), and shorting J10/J11 indicates slower 7MHz clocking in use.

J10/J11/J12 take on different meaning for the GuruROM V6 operations.  See the documentation provided with the GuruROM product.

Boards appear typically with a WD33C93A-04, or an AMD 33C93A (second source).  The AMD part is equal to a WD33C93A-08, but as far as the GVP FastROM 3.x/4.x or GuruROM V6, there is no functional or compatibility difference.

Unfortunately, the passive SCSI terminator packs are soldered in on the Series II SCSI PCBs.  Because of this, it is best to only use an internal or an external cabling solution with the HC8 at the one 'end' of the SCSI bus cabling.  The short 2" cable for the HardCard configuration usually is okay.

The boards do not supply termination (+5) power to the cable (bus).  Parts F1 and D1 to supply and restrict electrical back feed have markings on the PCB, but the parts are omitted.  Voltage direction for the diode is from the PCB to the SCSI cable/bus.

External SCSI off the DB25 needs to use proper shielded and twisted-pair (each singal with a ground) 50-wire SCSI cabling.  Use of a 25-wire parallel cable will not work.

All devices need to be given a unique SCSI ID.  The controller is always ID 7.  Given equal BootPri values in their RDB, the first bootable partition on the lowest SCSI ID present/ready will have first-in-line advantage to be the boot volume.

The 6MB setting provides for a chained 4MB and a 2MB AutoConfig memory board definition which will get merged together by OS 2.04 and later.  Under OS 1.2/1.3, the MergeMem command would need to be run to gain a contiguous ~6MB memory chunk.

Unique Logic Design (for a SCSI/RAM Controller)

The GVP DPRC - which stands for Dual Port RAM Controller, implements a semi-unique memory design taken from the original Amiga ChipRAM design (from a CPU->RAM perspective).  The memory operates at 14MHz, just like the Amiga ChipRAM.  Assuming both the CPU and the DMA controller want access to the FastRAM on the card, they alternate memory accesses on opposite clocks.  Agnus utilizes a similar solution with the CPU, although when it has more important duties, it can also steal access cycles from the main CPU, if needed.  Unlike Agnus, the DPRC does not steal bus cycles from the main CPU for DMA I/O transfers to the DPRC-controlled RAM.  The net result is that the DMA controller can transfer data at the full (7MHz equivalent) speed of a Zorro II bus on it's cycles, and the CPU can access that same memory on it's interleaved cycles, i.e. - they will never conflict.  This means that the OS and driver overhead, and other applications the CPU may be running, can continue while I/O to/from the disk interface can occur to the onboard FastRAM - all at the same time.  For a stock 68000 7MHz system, this provides a performance gain while the Amiga is under average and high I/O conditions.  Otherwise, DMA transfers off the HC8 PCB to any other 24-bit address in the system operates like a standard Amiga DMA controller.

For the above reason, it is impossible to 'bus snoop' for DMA transfers (same for ChipRAM, and the shared RAM on a Bridgecard or RTG video product) with products such as the AdSpeed or the Supra 28MHz 68000 accelerators.  The Amiga Zorro II bus, with many potential shared RAM regions and multiple bus masters, was not designed to support bus snooping, and attempting to do so breaks the hardware development rules.  Use the GVPSCSICtrl 68Cache kludge functionality to fix the design flaw in these two products.  Note: These products also fail to register their non-standard cache functionality with Kickstart 2.0+ OS's Pre/PostCacheDMA() functions, a documented developer requirement since OS 2.0, and will have probelms with the other share-memory expansion boards mentioned.

GVP's FastROM v3.x & v4.x driver, and the GuruROM V6, are fully 24/32-bit address-space and host environment aware.  They are highly compatible with nearly all SCSI devices with a reasonable grip on the SCSI I and SCSI II command and electrical specifications.  There is no need to modify the DMA Mask on partitions from the default full 0xFFFFFFFE value for any high-adressed 32-bit RAM.  The MaxTransfer default can always remain at the maximum 0x7FFFFFFF.  Modifications to partition these settings may be necessary if a disk is to be connected to another non-GVP controller with these kinds of limitations at another time.

If a DMA block limiter (for off-card DMA transfers) is needed, use the v4.x driver ROM and GVPSCSCtrl options and possibly GVPPatch (AmiNet).  This solves serial and parallel port interrupt latency issues, although the option can be used with any .device needing DMA transfers to be performed in smaller segments.

The GuruROM V6 and support tools have the same functionality as the V3/V4 FastROM driver and tools set, plus it gains some additional features.

Some RAM on the card is highly suggested for use in an A3000 or A4000, and with accelerators which have memory located above $00FF.FFFF (16MB), which is the 68000-based Amiga model's native 24-bit address space..  The last two gvpscsi.device releases, v4.14/4.15, will not DMA into ChipRAM due to the known bugs in some Super Buster + Zorro II DMA situations combined with some CPU accelerator cards.  The driver will seek out other 24-bit_DMA attributed RAM, if present, for buffering.  This can have a side effect of lowering the performance of transfers to ChipRAM on an A2000/A500 if the driver thinks it might be in an A3000 or A4000.  For this reason, use of gvpscsi.device v4.13 is preferred with the A2000, or A500, if a 68040 or 68060 CPU is operational in them.

The GuruROM V6 has the same ChipRAM DMA behavor as gvpscsi v4.14/4.15, but also has an override option in it's tool set to allow testing/override of the default behavior.  The omniscsi.device and gvpscsi.device will resort to Polled I/O transfers if a suitable 24-bit DMA-capable RAM buffer is not available, with a significant performance penalty.

Other DPRC Products and Series II Drivers

Aside from the SIMM memory slot differences, and fewer jumpers, the A500-HD8 product is functionally identical.  The Series II HC is related as far as the SCSI controller, but it has no memory options.  The A2000 RAM8/x is a Zorro II FastRAM memory-only variant.  Later GVP A2000 Combo/G-Force accelerators incorporate the SCSI-DMA functionality of this controller family. 

Several other products use the DPRC as a Zorro II bus interface for other common PC-XT chips on the market at the time.

OS 3.1.4/3.2.x - All v3/v4 gvpscsi.device drivers support the native 32-bit TD_ I/O functions, and the SCSI_Direct standard.  The third-party GuruROM V6 adds the TD_64 I/O functions and supports Sync SCSI communications when supported by target devices.  Heed the limitations of your choice of filesystems' versions and OS version(s).  Amiga OS 3.1.4 FFS supports SCSI_Direct and will operate with larger partitions (>2GB) and larger media (>4GB).  Earlier OS versions of FFS must heed the 2GB partition size and the 4GB media limit.  The original GVP FastPrep 2.51 and earlier will only handle the legacy 32-bit FFS partition and media limitations.  Use of the newer HDToolbox is suggested for OS 3.1.4/3.2.x and later.

AutoConfig Notes
- DPRC - 2017/11 64K (Generic - has additional non-standard extended information for driver ID)
- FastRAM 2/4/6/8 - 2017/10 (has 2x board entries for 6MB)
- DPRC tested functional outisde of the $E90000-$EFFFFF Z2 AutoConfig space.

For additional GVP V3/V4 driver information, there will be additional detail posted on the Combo/G-Force BBoAH pages.

BOM details from internal GVP documents can be found here: https://archive.org/details/gvp-a-4008-bom