Gemini Prototype
 connects to: Zorro III
Hi Res version, Front
- 1600 x 627, 272K
Hi Res version, Back
- 1600 x 621, 287K

Not strictly an accelerator but close enough! :) The Gemini was an attempt to build a multi-processor card designed for use on the Zorro III bus which contained two mini A3000s with 030's and 68882s as well as memory which would run a custom copy of exec. The Gemini could access all Zorro III memory and Chip RAM and each CPU could access the memory of the others. The board shown contains no CPU, FPU or RAMSEY. The board requires a Rev 11 buster since it uses "client" mode which allows it to be used as a board controller.

Updated info from Dave's, ebay auction march 2015:

This is a not-expected-to-function prototype from an in-house project at Commodore called Gemini. This board contains two Fat Busters, two 68030s, two 68852s, two RAMSEY chips, and room for about 4MB for each RAMSEY. There's also a bunch of control logic, buffers, etc. And some very neat rework wires on the back.

So, in 1992-1993, with Commodore basically in a patten of new management killing and delaying current projects and maybe-kinda-sorta thinking about replacing them with something worse, I had a little time on my hands. So I was working on the A4091, the "Acutiator" system architecture, the AAA prototype, and this board. I had been discussing dealing with multiprocessing with Randell Jesup, and we decided it would be a cool idea to build up an experiment. That's where Gemini came from.

This was also set to test an undocumented feature in the Fat Buster 2 chip. The ordinary Buster configuration had the Buster 2 acting as a 68030 to Zorro III bridge chip. But if you tied a few pins a certain way on reset, the chip would set itself up as reverse bridge. So, in theory, this would have the two 68030 system on it, with memory that could be accessed by the main processor via Zorro III. While technically a tightly coupled system, the plan was to treat this as a loosely coupled system, with a custom version of Exec and other AmigaOS elements running on each CPU. There was also a little memory trickery -- these mapped into normal Zorro III memory slots when autoconfigured, but each processor saw its own RAM at the same location, and mirrored at location 0 for vectors and booting, etc. And of course, more tricks could have been done with the MMU.

Aside from the initial bugs (those wires), much of this system was working. But v-e-r-y s-l-o-w-l-y. You can see the two Buster chips (far left) are CSG prototypes. This version of Buster was the crash-test-dummy for CSG's prototype of a sea of gates type gate array. Before that, the in-house gate arrays had been channeled arrays. This version of Fat Buster 2 (Rev 9 or 11, out there in the world) was necessary to run the reverse bus translation. And these parts ran at about 1/4 the rated speed. Ouch!

By the time the full-speed versions arrived, I was off doing other things, and of course, Commodore has been circling the drain, as more and more parts of the operation were subject to new management screw-ups. So I never got back to this. Obviously, you'd want faster processors at some point, but the software design would have been the same no matter what. Imagine an Amiga 4000T with eight additional 68040s or 68060s back in the mid 1990s. Ok, sure, and a souped-up power supply and liquid cooling :-)


Page contributors: Dave Haynie, Steen Jessen
Updated: 3/15/2015 . Added: 12/22/2004